CS5397 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5397 Datasheet PDF : 40 Pages
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CS5396 CS5397
SDATA2 - Digital Audio Data Output #2, Pin 15.
Stand-Alone Mode - The 24-bit low group delay audio data is presented MSB first, in 2’s
complement format.
Control Port Mode - The 24-bit low group delay audio data is presented MSB first, in 2’s
complement format. The audio data can be followed by 8 peak detect bits which indicate the
peak signal level. The additional audio data options include; the standard 24-bit word; 16, 18,
or 20-bit data with or without psychoacoustically optimized dither. The SDATA2 output is
completely independent from SDATA1.
Digital Inputs or Outputs
LRCK - Left/Right Clock, Pin 13.
LRCK determines which channel, left or right, is to be output on SDATA1 and SDATA2. In
master mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an
input whose frequency must be equal to Fs. Although the outputs for each channel are
transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs.
Stand-Alone Mode - The relationship between LRCK, SCLK and SDATA is controlled by the
Digital Format Select (DFS) pin.
Control Port Mode - The relationship between LRCK, SCLK and SDATA is controlled by the
control register.
SCLK - Serial Data Clock, Pin 14.
Stand-Alone Mode- Clocks the individual bits of the serial data from SDATA1 and SDATA2. In
master mode, SCLK is an output clock at 64x Fs. In slave mode, SCLK is an input which
requires a continuously supplied clock at any frequency from 48x to 128x Fs (64x is
recommended). The relationship between LRCK, SCLK and SDATA is controlled by the
Digital Format Select (DFS) pin.
Control Port Mode - Clocks the individual bits of the serial data from SDATA1 and SDATA2.
In master mode, SCLK is an output clock at 128x the output sample rate in the 128x
Oversampling Mode and 64x the output sample rate in the 64x Oversampling Mode.
In slave mode, SCLK is an input, which requires a continuously supplied clock at any
frequency from 32x to 128x the output sample rate. A 128x SCLK is preferred in the 128x
Oversampling Mode and 64x SCLK is preferred in the 64x Oversampling Mode. The
relationship between LRCK, SCLK and SDATA is controlled by the control register.
Miscellaneous
TSTO1, TSTO2 - Test Outputs, Pins 8 and 21.
These pins are intended for factory test outputs. They must not be connected to any external
component or any length of circuit trace.
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DS229PP2
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