CS5397 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5397 Datasheet PDF : 40 Pages
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CS5396 CS5397
AINL-, AINL+ - Differential Left Channel Analog Inputs, Pin 4,5.
Analog input connections for the left channel differential inputs. Nominally 4.0 Vpp differential
for full-scale digital output.
Analog Outputs
VCOM - Common Mode Voltage Output, Pin 2.
Nominally +2.5 volts. Requires a 100 µF electrolytic capacitor in parallel with 0.1 µF ceramic
capacitor for decoupling to AGND. Caution is required if this output is to be used to bias the
analog input buffer circuits. Refer to text.
VREF - Voltage Reference Output, Pin 1.
Nominally +4.0 volts. Requires a 470 µF electrolytic capacitor in parallel with 0.1 µF ceramic
capacitor for decoupling to AGND.
Digital Inputs
ADCTL - Analog Control Input, Pin 6.
Must be connected to DACTL. This signal enables communication between the analog and
digital circuits.
MCLKA - Analog Section Input Clock, Pin 7.
This clock is internally divided and controls the delta-sigma modulators. The required MCLKA
frequency is determined by the desired output sample rate (Fs). MCLKA of 24.576 MHz
corresponds to an Fs of 96 kHz in 64x Oversampling Mode and 48 kHz in 128x Oversampling
Mode.
MCLKD - Digital Section Input Clock, Pin 20.
MCLKD clocks the digital filter and must be connected to MCLKA. The required MCLKD
frequency is determined by the desired output sample rate (Fs). MCLKD of 24.576 MHz
corresponds to an Fs of 96 kHz in 64x Oversampling Mode and 48 kHz in 128x Oversampling
Mode.
Digital Input Pin Definitions for Stand-Alone MODE
DFS - Digital Format Select, Pin 18.
The relationship between LRCK, SCLK and SDATA is controlled by the DFS pin. When high,
the serial output data format is I2S compatible. The serial data format is left-justified when low.
PDN - Power-Down, Pin 19.
When high, the device enters power-down. Upon returning low, the device enters normal
operation. Calibration of the device is required following release of power-down.
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DS229PP2
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