CS4385(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS4385
(Rev.:2004)

114 dB, 192 kHz 8-Channel D/A Converter

Cirrus Logic 

CS4385

5.11 Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h)

7

xx_VOL7

0

6

xx_VOL6

0

5

xx_VOL5

0

4

xx_VOL4

0

3

xx_VOL3

0

2

xx_VOL2

0

1

xx_VOL1

0

0

xx_VOL0

0

These eight registers provide individual volume and mute control for each of the eight channels.

The values for “xx” in the bit fields above are as follows:

Register address 0Bh - xx = A1

Register address 0Ch - xx = B1

Register address 0Eh - xx = A2

Register address 0Fh - xx = B2

Register address 11h - xx = A3

Register address 12h - xx = B3

Register address 14h - xx = A4

Register address 15h - xx = B4

5.11.1 DIGITAL VOLUME CONTROL (XX_VOL7:0)

Default = 00h (0 dB)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments

from 0 to -127.5 dB. Volume settings are decoded as shown in Table 15. The volume changes are imple-

mented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that

the values in the volume setting column in Table 15 are approximate. The actual attenuation is determined

by taking the decimal value of the volume register and multiplying by 6.02/12.

Table 10. Example Digital Volume Settings

Binary Code

00000000

00000001

00000110

11111111

Decimal Value

0

1

6

255

Volume Setting

0 dB

-0.5 dB

-3.0 dB

-127.5 dB

5.12 PCM Clock Mode (address 16h)

7

Reserved

0

6

Reserved

0

5

MCLKDIV

0

4

Reserved

0

3

Reserved

0

2

Reserved

0

1

Reserved

0

0

Reserved

0

5.12.1 MASTER CLOCK DIVIDE BY 2 ENABLE (MCLKDIV)

Function:

When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2

prior to all other internal circuitry.

When set to 0 (default), MCLK is unchanged.

48

DS671A1

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