CS4385(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS4385
(Rev.:2004)

114 dB, 192 kHz 8-Channel D/A Converter

Cirrus Logic 

CS4385

3.12 Recommended Power-up Sequence

3.12.1 Hardware Mode

1. Hold RST low until the power supplies and configuration pins are stable, and the master

and left/right clocks are locked to the appropriate frequencies, as discussed in section 3.1.

In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ

will be connected to VA/2.

If RST can not be held low long enough the SDINx pins should remain static low until all

other clocks are stable, and if possible the RST should be toggled low again once the sys-

tem is stable.

2. Bring RST high. The device will remain in a low power state with FILT+ low and will ini-

tiate the Hardware power-up sequence after approximately 512 LRCK cycles in Single-

Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-

Speed Mode).

3.12.2 Software Mode

1. Hold RST low until the power supply is stable, and the master and left/right clocks are

locked to the appropriate frequencies, as discussed in section 3.1. In this state, the regis-

ters are reset to the default settings, FILT+ will remain low, and VQ will be connected to

VA/2.

2. Bring RST high. The device will remain in a low power state with FILT+ low for 512

LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048

LRCK cycles in Quad-Speed Mode).

3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior

to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK

cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The de-

sired register settings can be loaded while keeping the PDN bit set to 1.

If more than the stated number of LRCK cycles passes before CPEN bit is written then the

chip will enter Hardware mode and begin to operate with the M0-M4 as the mode settings.

CPEN bit may be written at anytime, even after the Hardware sequence has begun. It is

advised that if the CPEN bit can not be set in time then the SDINx pins should remain stat-

ic low (this way no audio data can be converted incorrectly by the hardware mode set-

tings).

4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately

50 µs.

30

DS671A1

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