C8051F98X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F98X

Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

Silicon Laboratories 

C8051F99x-C8051F98x

Table 4.4. Reset Electrical Characteristics

VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.

Parameter

Conditions

Min Typ Max Units

RST Output Low Voltage

RST Input High Voltage

RST Input Low Voltage

RST Input Pullup Current

IOL = 1.4 mA,

VDD = 2.0 to 3.6 V

VDD = 0.9 to 2.0 V

VDD = 2.0 to 3.6 V

VDD = 0.9 to 2.0 V

RST = 0.0 V, VDD = 1.8 V

RST = 0.0 V, VDD = 3.6 V

—

—

0.6

V

VDD – 0.6 —

—

V

0.7 x VDD —

—

V

—

—

0.6

V

—

— 0.3 x VDD V

—

4

—

µA

—

20

30

VDD Monitor Threshold

(VRST)

Early Warning

Reset Trigger

(all power modes except Sleep)

1.8 1.85 1.9

V

1.7 1.75 1.8

VDD Ramp Time for Power

On

VBAT Ramp from 0–1.8 V

—

—

3

ms

POR Monitor Threshold

Brownout Condition (VDD Falling)

0.45 0.7 1.0

(VPOR)

V

Recovery from Brownout (VDD Rising) — 1.75 —

Missing Clock Detector

Timeout

Time from last system clock rising edge

to reset initiation

100

650 1000

µs

Minimum System Clock w/ System clock frequency which triggers

Missing Clock Detector

a missing clock detector timeout

—

7

10

kHz

Enabled

Reset Time Delay

Delay between release of any reset

source and code

execution at location 0x0000

—

10

—

µs

Minimum RST Low Time to

Generate a System Reset

15

—

—

µs

VDD Monitor Turn-on Time

VDD Monitor Supply 

Current

—

300

—

ns

—

7

—

µA

Rev. 1.0

55

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