C8051F91X-C8051F90X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

outputs during sleep mode, then the VDD/DC+ output can be made to float during Sleep mode by setting

the VDDSLP bit in the DC0CF register to 1.

Setting this bit can provide power savings in two ways. First, if the sleep interval is relatively short and the

VDD/DC+ load current (include leakage currents) is negligible, then the capacitor on VDD/DC+ will main-

tain the output voltage near the programmed value, which means that the VDD/DC+ capacitor will not need

to be recharged upon every wake up event. The second power advantage is that internal or external low-

power circuits that require more than 1.8 V can continue to function during Sleep mode without operating

the dc-dc converter, powered by the energy stored in the 1 µF output decoupling capacitor. For example,

the C8051F91x-C8051F90x comparators require about 0.4 µA when operating in their lowest power mode.

If the dc-dc converter output were increased to 3.3 V just before putting the device into Sleep mode, then

the comparator could be powered for more than 3 seconds before the output voltage dropped to 1.8 V. In

this example, the overall energy consumption would be much lower than if the dc-dc converter were kept

running to power the comparator.

If the load current on VDD/DC+ is high enough to discharge the VDD/DC+ capacitance to a voltage lower

than VBAT during the sleep interval, an internal diode will prevent VDD/DC+ from dropping more than a

few hundred millivolts below VBAT. There may be some additional leakage current from VBAT to ground

when the VDD/DC+ level falls below VBAT, but this leakage current should be small compared to the cur-

rent from VDD/DC+.

The amount of time that it takes for a device configured in one-cell mode to wake up from Sleep mode

depends on a number of factors, including the dc-dc converter clock speed, the settings of the SWSEL,

ILIMIT, and LPEN bits, the battery internal resistance, the load current, and the difference between the

VBAT voltage level and the programmed output voltage. The wake up time can be as short as 2 µs, though

it is more commonly in the range of 5 to 10 µs, and it can exceed 50 µs under extreme conditions.

See Section “14. Power Management” on page 143 for more information about sleep mode.

16.9. Bypass Mode (C8051F912/02 only)

During normal operation, if the dc-dc converter input voltage exceeds the programmed output voltage, the

converter will stop switching and the Diode Bypass switch will remain in the “on” state. The output voltage

will be equal to the input voltage minus any resistive loss in the switch and all of the converter’s analog cir-

cuits will remain biased. The bypass feature automatically shuts off the dc-dc converter when the input

voltage is greater than the programmed output voltage by 150 mV. In bypass, the Diode Bypass switch and

dc-dc converter bias currents are disabled except for the voltage comparison circuitry (~ 3 µA, depending

on the configuration settings in the DC0MD register). If the input voltage drops within 50 mV of the pro-

grammed output value, then the dc-dc converter automatically starts operating in the normal state. There is

100 mV voltage hysteresis built in the bypass comparator to enhance stability.

The bypass mode increases system operating time in systems which have a minimum operating voltage

higher than the battery end of life voltage. For instance, if an external chip requires a minimum supply volt-

age of 2.7 V and a lithium coin cell battery is used as power source (end-of-life voltage is approximately

2 V), then the C8051F912/902’s dc-dc converter could be configured for an output voltage of 2.7 V with

bypass mode enabled. The dc-dc converter would be bypassed when the battery was fresh, but as soon

as the battery voltage dropped below 2.75 V, the dc-dc converter would turn on to ensure that the external

chip was provided with a minimum of 2.7 V for the remainder of the battery life.

16.10. Low Power Mode (C8051F912/02 only)

Setting the LPEN bit in the DC0CF register will enable a Low Power Mode for the dc-dc converter. In Low

Power Mode, the bias currents are substantially reduced, which can lead to an efficiency improvement with

light load currents (generally less than a few mA). The drawback to this mode is that the response time of

the converter’s analog blocks is increased; larger delay in the circuits controlling the Diode Bypass switch

can lead to loss of efficiency at medium and high load currents due to reverse leakage in the switch. The

Low power mode also reduces the peak inductor current limit as shown in Table 16.1.

Rev. 1.0

165

Share Link: