C8051F38C-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F38C-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

TMR3CN

TTTTTTTT

FFF 3 3R3 3

3 3 3CS3CX

HL LEP SC

E L SL

NI K

T

SYSCLK / 12

0

External Clock / 8

1

SYSCLK

CKCON

TTTTTTSS

3 3 2 2 1 0CC

MMMMMMA A

HLHL 10

0

TR3

1

TCLK TMR3L TMR3H

To ADC

USB Start-of-Frame (SOF)

Low-Frequency Oscillator

Falling Edge

0

Capture TMR3RLL TMR3RLH

1

T3CSS Enable

Interrupt

Figure 26.10. Timer 3 Capture Mode (T3SPLIT = 0)

When T3SPLIT = 1, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter

counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-

tents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A

Timer 3 interrupt is generated if enabled.

Rev. 1.4

283

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