C8051F38C-GMR View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F38C-GMR Datasheet PDF : 321 Pages
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C8051F380/1/2/3/4/5/6/7/C
26.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is 1 and T3CE = 0, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit
timers operate in auto-reload mode as shown in Figure 26.9. TMR3RLL holds the reload value for TMR3L;
TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H.
TMR3L is always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
T3MH
0
0
1
T3XCLK
0
1
X
TMR3H Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
T3ML
0
0
1
T3XCLK
0
1
X
TMR3L Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
T3XCLK
SYSCLK / 12
0
External Clock / 8
1
SYSCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
TMR3RLH Reload
0
TR3
TCLK TMR3H
1
TMR3RLL Reload
To ADC
TF3H
TF3L
TF3LEN
T3CE
T3SPLIT
TR3
T3CSS
T3XCLK
Interrupt
1
TCLK TMR3L
0
Figure 26.9. Timer 3 8-Bit Mode Block Diagram
26.3.3. Timer 3 Capture Modes: USB Start-of-Frame or LFO Falling Edge
When T3CE = 1, Timer 3 will operate in one of two special capture modes. The capture event can be
selected between a USB Start-of-Frame (SOF) capture, and a Low-Frequency Oscillator (LFO) Falling
Edge capture, using the T3CSS bit. The USB SOF capture mode can be used to calibrate the system clock
or external oscillator against the known USB host SOF clock. The LFO falling-edge capture mode can be
used to calibrate the internal Low-Frequency Oscillator against the internal High-Frequency Oscillator or
an external clock source. When T3SPLIT = 0, Timer 3 counts up and overflows from 0xFFFF to 0x0000.
Each time a capture event is received, the contents of the Timer 3 registers (TMR3H:TMR3L) are latched
into the Timer 3 Reload registers (TMR3RLH:TMR3RLL). A Timer 3 interrupt is generated if enabled.
282
Rev. 1.4
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