C8051F362-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F362-GM

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

complete Port I/O configuration details. The TEMPE bit in register REF0CN enables/disables the tempera-

ture sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0

measurements performed on the sensor result in meaningless data.

SFR Definition 7.1. REF0CN: Reference Control

SFR Page: all pages

SFR Address: 0xD1

R

R

R

R

R/W

R/W

R/W

R/W

Reset Value

–

–

–

–

REFSL TEMPE BIASE REFBE 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits 7–4: UNUSED. Read = 0000b; Write = don’t care.

Bit 3: REFSL: Voltage Reference Select.

This bit selects the source for the internal voltage reference.

0: VREF pin used as voltage reference.

1: VDD used as voltage reference.

Bit 2: TEMPE: Temperature Sensor Enable Bit.

0: Internal Temperature Sensor off.

1: Internal Temperature Sensor on.

Bit 1: BIASE: Internal Analog Bias Generator Enable Bit.

0: Internal Bias Generator off.

1: Internal Bias Generator on.

Bit 0: REFBE: Internal Reference Buffer Enable Bit.

0: Internal Reference Buffer disabled.

1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.

68

Rev. 1.0

Share Link: