C8051F364 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F364

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

11. Multiply And Accumulate (MAC0)

The C8051F36x devices include a multiply and accumulate engine which can be used to speed up many

mathematical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform

integer or fractional multiply-accumulate and multiply operations on signed input values in two SYSCLK

cycles. A rounding engine provides a rounded 16-bit fractional result after an additional (third) SYSCLK

cycle. MAC0 also contains a 1-bit arithmetic shifter that will left or right-shift the contents of the 40-bit accu-

mulator in a single SYSCLK cycle. Figure 11.1 shows a block diagram of the MAC0 unit and its associated

Special Function Registers.

MAC0 A Register

MAC0AH MAC0AL

MAC0 B Register

MAC0BH MAC0BL

MAC0FM 16 x 16 Multiply

40 bit Add

MAC0MS

1

0

0

MAC0 Accumulator

MAC0OVR MAC0ACC3 MAC0ACC2 MAC0ACC1 MAC0ACC0

1 bit Shift

Rounding Engine

Flag Logic

MAC0 Rounding Register

MAC0RNDH MAC0RNDL

MAC0CF

MAC0STA

Figure 11.1. MAC0 Block Diagram

11.1. Special Function Registers

There are thirteen Special Function Register (SFR) locations associated with MAC0. Two of these regis-

ters are related to configuration and operation, while the other eleven are used to store multi-byte input

and output data for MAC0. The Configuration register MAC0CF (SFR Definition 11.1) is used to configure

and control MAC0. The Status register MAC0STA (SFR Definition 11.2) contains flags to indicate overflow

conditions, as well as zero and negative results. The 16-bit MAC0A (MAC0AH:MAC0AL) and MAC0B

(MAC0BH:MAC0BL) registers are used as inputs to the multiplier. The MAC0 Accumulator register is 40

bits long, and consists of five SFRs: MAC0OVR, MAC0ACC3, MAC0ACC2, MAC0ACC1, and

MAC0ACC0. The primary results of a MAC0 operation are stored in the Accumulator registers. If they are

needed, the rounded results are stored in the 16-bit Rounding Register MAC0RND

(MAC0RNDH:MAC0RNDL).

Rev. 1.0

117

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