C8051F364 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F364

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 10.5. EIE2: Extended Interrupt Enable 2

SFR Page: all pages

SFR Address: 0xE7

R/W

R/W

–

–

Bit7

Bit6

R/W

–

Bit5

R/W

–

Bit4

R/W

–

Bit3

R/W

–

Bit2

Bits 7–2: UNUSED. Read = 000000b. Write = don’t care.

Bit 1: EMAT: Enable Port Match Interrupt.

This bit sets the masking of the Port Match interrupt.

0: Disable the Port Match interrupt.

1: Enable the Port Match interrupt.

Bit 0: UNUSED. Read = 0b. Write = don’t care.

R/W

EMAT

Bit1

R/W

Reset Value

–

00000000

Bit0

SFR Definition 10.6. EIP2: Extended Interrupt Priority 2

SFR Page: F

SFR Address: 0xCF

R/W

R/W

–

–

Bit7

Bit6

R/W

–

Bit5

R/W

–

Bit4

R/W

–

Bit3

R/W

–

Bit2

Bits 7–2: UNUSED. Read = 000000b. Write = don’t care.

Bit 1: PMAT: Port Match Interrupt Priority Control.

This bit sets the priority of the Port Match interrupt.

0: Port Match interrupt set to low priority level.

1: Port Match interrupt set to high priority level.

Bit 0: UNUSED. Read = 0b. Write = don’t care.

R/W

PMAT

Bit1

R/W

Reset Value

–

00000000

Bit0

114

Rev. 1.0

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