ACS8522AT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8522AT Datasheet PDF : 118 Pages
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ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Figure 11 Control of 8k Options.
03 output
FrSync/8kHz output
a) Clock non-inverted, Reg.7A[3:2] = 00
FINAL
DATASHEET
03 output
FrSync/8kHz output
c) Clock inverted, Reg.7A[3:2] = 10
03 output
FrSync/8kHz output
b) Pulse non-inverted, Reg.7A[3:2] = 01
Table 17 Digital Frequency Selections
Digital1 Control
Reg.39 Bits [5:4]
Digital1 SONET/ Digital1 Freq. (MHz)
SDH Reg. 38 Bit5
00
0
2.048
01
0
4.096
10
0
8.192
11
0
16.384
00
1
1.544
01
1
3.088
10
1
6.176
11
1
12.352
03 output
FrSync/8kHz output
d) Pulse inverted, Reg.7A[3:2] = 11
F8522_016outputoptions8k_01
Digital2 Control
Reg. 39 Bits[7:6]
00
01
10
11
00
01
10
11
Digital2 SONET/SDH Digital2 Freq. (MHz)
Reg.38 Bit6
0
2.048
0
4.096
0
8.192
0
16.384
1
1.544
1
3.088
1
6.176
1
12.352
Power-On Reset
The Power-On Reset (PORB) pin resets the device if forced
Low. The reset is asynchronous, the minimum Low pulse
width is 5 ns. Reset is needed to initialize all of the
register values to their defaults. Reset must be asserted
at power on, and may be re-asserted at any time to restore
defaults. This is implemented simply using an external
capacitor to GND along with the internal pull-up resistor.
The ACS8522A is held in a reset state for 250 ms after the
PORB pin has been pulled High. In normal operation PORB
should be held High.
ACS8522A address and data are transmitted and
received LSB first. Address, read/write control and data
on the SDI pin are latched into the device on the rising
edge of the SCLK. During a read operation, serial data
output on the SDO pin can be read out of the device on
either the rising or falling edge of the SCLK depending on
the logic level of CLKE. For standard Motorola SPI
compliance, data should be clocked out of the SDO pin on
the rising edge of the SCLK so that it may be latched into
the microprocessor on the falling edge of the SCLK.
Figure 12 and Figure 13 show the timing diagrams of
write and read accesses for this interface.
Serial Interface
The ACS8522A device has a serial interface which can be
SPI compatible.
During read access, the output data SDO is clocked out on
the rising edge of SCLK when the active edge selection
control bit CLKE is 0 and on the falling edge when CLKE is
1.
The Motorola SPI convention is such that address and
data is transmitted and received MSB first. On the
The serial interface clock (SCLK) is not required to run
between accesses (i.e., when CSB = 1).
Revision 1.00/September 2007 © Semtech Corp.
Page 38
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