ACS8522AT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8522AT Datasheet PDF : 118 Pages
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ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Table 16 O1 to O4 Output Frequency Selection
FINAL
DATASHEET
Output Frequency for given “Value in Register” for each Output Port’s cnfg_output_frequency Register
Value in Register
0000
O1, Reg. 62 Bits [7:4] O2, Reg. 60 Bits [7:4] O3, Reg. 61 Bits [3:0] O4, Reg. 62 Bits [3:0]
Off
Off
Off
Off
0001
2 kHz
2 kHz
2 kHz
2 kHz
0010
0011
0100
8 kHz
T0 APLL/2
Digital1
8 kHz
Digital2
Digital1
8 kHz
Digital2
Digital1
8 kHz
Digital2
Digital1
0101
T0 APLL/1
T0 APLL/48
T0 APLL/48
T0 APLL/48
0110
0111
1000
1001
T0 APLL/16
T0 APLL/12
T0 APLL/8
T0 APLL/6
T0 APLL/16
T0 APLL/12
T0 APLL/8
T0 APLL/6
T0 APLL/16
T0 APLL/12
T0 APLL/8
T0 APLL/6
T0 APLL/16
T0 APLL/12
T0 APLL/8
T0 APLL/6
1010
T0 APLL/4
T0 APLL/4
T0 APLL/4
T0 APLL/4
1011
1100
1101
T4 APLL/64
T4 APLL/48
T4 APLL/16
T4 APLL/64
T4 APLL/48
T4 APLL/16
T4 APLL/64
T4 APLL/48
T4 APLL/16
T4 APLL/2
T4 APLL/48
T4 APLL/16
1110
T4 APLL/8
T4 APLL/8
T4 APLL/8
T4 APLL/8
1111
T4 APLL/4
T4 APLL/4
T4 APLL/4
T4 APLL/4
“Digital” Frequencies
FrSync, MFrSync, 2 kHz and 8 kHz Clock Outputs
It can be seen from Table 16 (O1 to O4 output frequency
selection) that frequencies listed as Digital1 and Digital2
can be selected. Digital1 is a single frequency selected
from the range shown in Table 17. Digital2 is another
single frequency selected from the same range. The T0 LF
output DFS block shown in the diagram and clocked
either by the T0 77M output DFS block or via the T0
output APLL, generates these two frequencies. The input
clock frequency of the DFS is always 77.76 MHz and as
such has a period of approximately 12 ns. The jitter
generated on the Digital outputs is relatively high, due to
the fact that they do not pass through an APLL for jitter
filtering. The minimum level of jitter is when the T0 path is
in analog feedback mode, when the pk-pk jitter will be
approximately 12 ns (equivalent to a period of the DFS
clock). The maximum jitter is generated when in digital
feedback mode, when the total is approximately 17 ns.
It can be seen from Table 16 (O1 to O4 Output Frequency
Selection) that frequencies listed as 2 kHz and 8 kHz can
be selected. Whilst the FrSync and MFrSync outputs are
always supplied from the T0 path, the 2 kHz and 8 kHz
options available from the O1 to O4 outputs are all
supplied from either the T0 or T4 path (Reg. 7A bit 7).
The outputs can be either clocks (50:50 mark-space) or
pulses and can be inverted. When pulses are configured
on the output, the pulse width will be one cycle of the
output of O3 (O3 must be configured to generate at least
1544 kHz to ensure that pulses are generated correctly).
Figure 11 shows the various options with the 8 kHz
controls in Reg. 7A. There is an identical arrangement
with Reg. 7A bits [1:0] and the 2 kHz/MFrSync outputs.
Outputs FrSync and MFrSync can be disabled via Reg. 63
bits [7:6].
Revision 1.00/September 2007 © Semtech Corp.
Page 37
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