ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
Data Sheet
TABLE 3-1: Pin Assignments (Continued) (3 of 4)
Pin No.
Symbol
85-
84-
100-TQFP VFBGA TFBGA
Serial Communication Interface (SCI)
SCIDOUT
79
J2
A9
SCIDIN
78
K2
C8
SCICLK
77
K1
C9
Pin
Type
O
I
I
I/O
Type1
O4
I3U
I3U
Name and Functions
SCI interface data output
SCI interface data input
SCI interface clock
External Clock Option
FCE7#/
26
INTCLKEN
C9
J1 I/O I3D/O4 Active Low Flash Media Chip Enable pin
This pin is sensed during the Power-on Reset (POR) to select
an Internal Clock mode. If this pin is pulled up during the
Power-on Reset then the Internal Clock is selected.
EXTCLKIN
100
J8
B3
I
I4Z External Clock source input pin
EXTCLKOUT
99
K9
A3
O
O4 External Clock source output pin
Miscellaneous
VSS (IO)
2
A2
12
A6
27
A10
36
D4
64
74
E1
E10
D7, G4 PWR
90
H1
98
J10
K5
K8
Ground for I/O
VSS (Core)
25
51
A1
B10
G7 PWR
Ground for Core
VDD (IO)
38
B6
87
K4
K4 PWR
VDD (3.3V)
VDD (Core)
76
VDDQ (IO)
7
69
J1
B9 PWR
F1
G10
B1 PWR
VDD (3.3V)
VDDQ (5V/3.3V) for Host interface
POR#
50
B3
H7
I Analog Power-on Reset (POR). Active Low
Input2
TIE_DN
13
D1
Pins need to be connected to VSS.
©2006 Silicon Storage Technology, Inc.
12
S71241-04-000
12/06