Display RAM address and display mode
4
Display RAM address and display mode
STFPC311
Note:
The display RAM stores the data transmitted from an external device to the STFPC311
through the serial interface and is assigned addresses, in units of 8-bits see Table 3.
Only the lower 4 bits of the addresses assigned to Seg17 through Seg20 are valid, the higher
4 bits are ignored.
The common grid/segment outputs are grid-based. The grid has to be enabled before any
segments can be turned on. If data is written for a segment before enabling its grid, there is
nothing on the display.
Table 3. Assigned addresses
t(s) Seg1
Seg4
Seg8
c 00 HL
du 03 HL
ro 06 HL
te P 09 HL
le 0C HL
so 0F HL
b 12 HL
- O 15 HL
t(s) 18 HL
c 1B HL
du 1E HL
ro 21 HL
te P 24 HL
le 27 HL
so 2A HL
Ob 2D HL
00 HU
03 HU
06 HU
09 HU
0C HU
0F HU
12 HU
15 HU
18 HU
1B HU
1E HU
21 HU
24 HU
27 HU
2A HU
2D HU
01 HL
04 HL
07 HL
0A HL
0D HL
10 HL
13 HL
16 HL
19 HL
1C HL
1F HL
22 HL
25 HL
28 HL
2B HL
2E HL
Seg12
Seg16
Seg20
01 HU
04 HU
07 HU
0A HU
0D HU
10 HU
13 HU
16 HU
19 HU
1C HU
1F HU
22 HU
25 HU
28 HU
2B HU
2E HU
02 HL
05 HL
08 HL
0B HL
0E HL
11 HL
14 HL
17 HL
1A HL
1D HL
20 HL
23 HL
26 HL
29 HL
2C HL
2F HL
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
DIG10
DIG11
DIG12
DIG13
DIG14
DIG15
DIG16
b0
b3 b4
b7
XX HL
XX HU
Lower 4 bits Higher 4 bits
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Doc ID 12324 Rev 2