CS62180A-IL View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS62180A-IL

T1 Framer

Cirrus Logic 

CS62180A

CS62180B

Transmitter

Inputs

TCLK - Transmit Clock, Pin 3 (PLCC, Pin 4).

1.544 MHz primary transmitter clock. Divided down internally to provide timing signals. TPOS

and TNEG are updated on the rising edge of TCLK. Input transmission data (TSER, TABCD,

and TLINK) is sampled on the falling edge of TCLK.

A 1.544 MHz signal must be input into TCLK even for those applications where the transmitter

is not being used. TCLK is used by the circuitry which clears status registers after those regis-

ters have been directly read (non-burst mode read).

TMSYNC - Transmit Multiframe Sync, Pin 1 (PLCC, Pin 1).

A low to high transition of TMSYNC, occurring near the rising edge of TCLK, resets transmit-

ter’s frame and multiframe counters, identifying bit period (at TSER) concurrent with the next

falling edge of TCLK as the F-bit of frame 1. If tied low, TFSYNC may be used to set frame

alignment, and the CS62180A and CS62180B will arbitrarily choose multiframe alignment.

Internal channel, frame, and multiframe counters are output on TCHCLK, TMO, TSIGSEL,

TSIGFR, and TLCLK.

TFSYNC - Transmit Frame Sync, Pin 2 (PLCC, Pin 2).

A low to high transition of TFSYNC, occurring near the rising edge of TCLK, resets transmit-

ter’s frame counters, identifying bit period (at TSER) concurrent with the next falling edge of

TCLK as the F-bit of a new frame. If tied low, TMSYNC may be used to set both frame and

multiframe alignment. Without any sync input, the CS62180A and CS62180B will arbitrarily

choose both frame and multiframe alignment. Internal channel, frame, and multiframe counters

are output on TCHCLK, TMO, TSIGSEL, TSIGFR, and TLCLK.

TSER - Transmit Serial Data, Pin 5 (PLCC, Pin 7).

Input data (NRZ format), sampled on the falling edge of TCLK. TSER may also be used to

provide externally supplied data for insertion into FT, FPS, and CRC channels. Refer to Trans-

mit Control Register, bits 5 and 6. Delay from TSER to TPOS/TNEG is 10 TCLK periods.

TABCD - Transmit ABCD Signaling, Pin 9 (PLCC, Pin 11).

When enabled, by setting bit 4 of the Transmit Control Register (TCR), data provided on

TABCD is inserted into the 8th bit position (LSB) of every DS0 channel during signaling

frames. Those are frames 6 and 12 in 193S format, and 6, 12, 18, and 24 in 193E. Signaling on

individual DS0 channels may be suppressed by declaring those channels transparent in the

Transmit Transparent Registers (TTR). Signaling in hardware mode is always enabled. Delay

from TABCD to TPOS/TNEG is 10 TCLK periods.

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DS225PP1

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