CS62180A-IL View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS62180A-IL

T1 Framer

Cirrus Logic 

CS62180A

CS62180B

7 (MSB)

BVD7

6

5

4

3

2

1

0 (LSB)

BVD6 BVD5 BVD4 BVD3 BVD2 BVD1 BVD0

Counts individual Bipolar Violations. Sets RSR.7 high when overfolws past 255 (11111111).

Presetable to any starting value to limit the number of Bipolar Violations needed to overflow.

Figure 24. Bipolar Violation Count Register (BVCR)

7 (MSB)

BVCS

0

1

6

5

4

3

2

1

ECS RYEL RCL FERR B8ZSD RBL

Disables interrupts for the corresponding bit of the RSR.

Enables an interrupt whenever the corresponding bit of the RSR goes high.

0 (LSB)

RLOS

Figure 25. Receive Interrupt Mask Register (RIMR)

Violation received will cause BVCS (RSR.7) to

be set to a "1". The BVCR can be preset, to a

value greater than 0, to lower the threshold at

which it saturates and signals an alarm in RSR.7.

Bipolar Violations in valid B8ZS codes are never

counted by the CS62180B, but will be counted

by the CS62180A if B8ZS format is disabled via

CCR.2. Note also that the Bipolar Violation

monitoring circuit is disabled entirely when us-

ing NRZ input at RPOS/RNEG (selected by

tying RPOS/RNEG together).

Individual Bipolar Violations are also reported in

real time on RBV (pin 37). RBV will go high

simultaneously with the output of the accused bit

at RSER. It will only be held for that bit period,

falling at the next bit, unless another violation is

detected.

Interrupts

When operating in host mode, an interrupt pin,

INT (pin 14), is provided to signal the host proc-

essor of alarm conditions. INT is an open drain

output, and should be tied to the positive supply

through a resistor. The INT pin can be pro-

grammed to respond whenever any bit of the

Receive Status Register (RSR) goes high by set-

ting the corresponding bit of the Receive

Interrupt Mask Register (RIMR). Each bit of the

RIMR is ’AND’ed with the corresponding bit of

the RSR to determine the interrupt. Clearing any

bit in the RIMR will disable the interrupt for that

alarm condition. When an interrupt has been sig-

naled, the CS62180A and CS62180B must be

serviced by the host processor to clear the alarm,

as described below. Figure 25 shows an overview

of the RIMR.

Alarm Servicing

The CS62180A and CS62180B must be serviced

by the host processor to clear the interrupt.

Clearing the appropriate bit (or bits, if more than

1 alarm condition exists) in the Receive Interrupt

Mask Register (RIMR) will clear any interrupt

unconditionally. The interrupt for that alarm will

remain disabled until the bit in the RIMR is set

again.

Depending on the type of alarm condition, an in-

terrupt may also be cleared without changing the

RIMR. If the alarm is in response to a counter

saturation (see Bipolar Violation Count Satura-

tion and Error Count Saturation, above), then

the counter must be reset to a value other than

all "1’s" to clear the alarm. If the interrupt is in

response to a real time event, then it may be

cleared by a direct read (a burst read will have

no effect) of the RSR. Note that reading the RSR

will only clear the interrupt if the alarm condi-

tion no longer persists. For real time events of

long duration, clearing the appropriate bits in the

RIMR is the only way to clear the interrupt.

32

DS225PP1

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