
CL-PS7500FE
System-on-a-Chip for Internet Appliance
LA[28:0]
I_OCLK
ta d d 3
ta d d 2
CLK16
IORNW
nPCCS1
ti o r n w l
tc s l _ p c
ti o r n w l
tc s h _ p c
nIOR
tn i o r l
tn i o r h
READY
BD[15:0]
tr d s
Upper
Lower
tr d h
nPCCS1
tx l s
tx l h
Figure 22-22. 16-MHz Type B I/O Read Cycle Timing with PCMCIA
218
ELECTRICAL SPECIFICATIONS
ADVANCE DATA BOOK v2.0
June 1997