STPCE1EDBI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STPCE1EDBI Datasheet PDF : 87 Pages
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ELECTRICAL SPECIFICATIONS
4.5.3. SDRAM INTERFACE
Figure 4-5 and Table 4-8 list the AC characteris-
tics of the SDRAM interface. The MCLKx clocks
are the input clock of the SDRAM devices
Figure 4-5. SDRAM Timing Diagram
MCLKx
MCLKI
STPC.output
Tdelay
Thigh
Tcycle
Tlow
Toutput (max)
Toutput (min)
STPC.input
Thold
Tsetup
Table 4-8. SDRAM Bus AC Timing
Name Parameter
Tcycle MCLKI Cycle Time
Thigh MCLKI High Time
Tlow MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
Tdelay MCLKx to MCLKI delay
MCLKI to Outputs Valid
Toutput MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
Tsetup MD[63:0] setup to MCKLI without RDCLK
Thold MD[63:0] hold from MCKLI without RDCLK
Note: These timing are for a load of 50pF.
The PC133 memory is recommended to reach
100MHz operation.
Min Typ Max Unit
10
ns
4
ns
4
ns
1
ns
1
ns
-2
ns
5.2
8.7
ns
4.7
10.9 ns
5.1
10.9 ns
0.8
1.8
ns
0.8
1.6
ns
40/87
Release 1.3 - January 29, 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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