STPCE1EDBI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STPCE1EDBI Datasheet PDF : 87 Pages
| |||
3.1.4. HCLK STRAP REGISTER CONFIGURATION
STRAP OPTION
HCLK_Strap
Access = 0022h/0023h
Regoffset = 05Fh
7
6
5
4
3
2
1
0
MD3
MD2
MD26
MD25
MD24
Rsv
This register defaults to the values sampled on MD[3:2] and MD[26:24] pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-3
These bits reflect the values sampled on MD[3:2] and MD[26:24] pins
MD[3:2] & [26:24] respectively and control the Host clock frequency synthesizer, as given
in Table 3-4.
Bits 2-0
Rsv
Reserved
Bit 7
0
0
0
0
0
0
1
1
Bit 6
0
0
0
0
1
1
0
1
Table 3-4. HCLK Frequency
Bit 5
0
0
0
0
0
1
0
0
Bit 4
0
0
1
1
0
1
1
0
Bit 3
0
1
0
1
1
0
1
1
HCLK Frequency
25 MHz
50 MHz
60 MHz
66 MHz
75 MHz
82.5 MHz
90 MHz
100 MHz
Release 1.3 - January 29, 2002
31/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Share Link: 