STPCI2GDYI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STPCI2GDYI

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

The maximum skew between pins for this part is 6.4.3.4. Summary

250ps. The important factors for the clock buffer

are a consistent drive strength and low skew For unbuffered DIMMs the address/control signals

between the outputs. The delay through the buffer will be the most critical for timing. The simulations

is not important so it does not have to be a zero show that for these signals the best way to drive

delay PLL type buffer. The trace lengths from the them is to use a parallel termination. For

clock driver to the DIMM CKn pins should be applications where speed is not so critical series

matched exactly. Since the propagation speed can termination can be used as this will save power.

vary between PCB layers, the clocks should be Using a low impedance such as 50Ω for these

routed in a consistent way. The routing to the critical traces is recommended as it both reduces

STPC memory input should be longer by 75 mm to the delay and the overshoot.

compensate for the extra clock routing on the

DIMM. Also a 20 pF capacitor should be placed as The other memory interface signals will typically

near as possible to the clock input of the STPC to be not as critical as the address/control signals.

compensate for the DIMM’s higher clock load. The Using lower impedance traces is also beneficial for

impedance of the trace used for the clock routing the other signals but if their timing is not as critical

. should be matched to the DIMM clock trace as the address/control signals they could use the

impedance (60-75 ohms) To minimise crosstalk default value. Using a lower impedance implies

the clocks should be routed with spacing to using wider traces which may have an impact on

adjacent tracks of at least twice the clock trace

) width. For designs which use SDRAMs directly

t(s mounted on the motherboard PCB all the clock

trace lengths should be matched to the constraints

c given in Figure 6-23 and in Section 4.5.3. .

the routing of the board.

The layout of this interface can be validated by an

electrical simulation using the IBIS model

available on the STPC web site.

du The DIMM sockets should be populated starting

ro with the furthest DIMM from the STPC device first

(DIMM1). There are two types of DIMM devices;

P single-row and dual-row. The dual-row devices

te require two chip select signals to select between

the two rows. A STPC device with 4 chip select

le control lines could control either 4 single-row

o DIMMs or 2 dual-row DIMMs. When only 2 chip

s select control lines are activated, only two single-

b row DIMMs or one dual-row DIMM can be

O controlled.

6.5. CLOCK TOPOLOGY FOR ON-BOARD

SDRAM

Figure 4-5 and Figure 6-25 give the recommended

clock topology and the resulting IBIS simulation in

the case of four on-board SDRAM devices and no

clock buffer.

- Figure 6-24. Recommended topology for 4 on-board SDRAMs (IBIS model)

uct(s) MCLKO

Obsolete Prod MCLKI

400 mils

400 mils

18 Ohms

3500 mils

3500 mils

MCLK0

MCLK1

Track impedance= 75 Ohms

Trace thickness = 0.72 mil

Trace width = 4 to 8 mils

3500 mils

3500 mils

MCLK2

MCLK3

93/108

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