STPCI2GDYI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STPCI2GDYI Datasheet PDF : 108 Pages
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STPC® ATLAS
Figure 6-22. DIMM placement
35mm
STPC
35mm
SDRAM I/F
15mm
DIMM2
DIMM1
ct(s) 116mm
10mm
rodu SDRAM components and the memory controller
P will impact the timing budget. In order to get well
matched clocks at all components it is
te recommended that all the DIMM clock pins, STPC
le memory clock input (MCLKI) and any other
o component using the memory clock are
s individually driven from a low skew clock driver
b with matched routing lengths specified in Section
4.5.3. . In other words, all clock line lengths that go
- O Figure 6-23. Clock Routing
from the buffer to the memory chips (MCLKx) and
from the buffer to the STPC (MCLKI) must follow
this equation;
MCLKx = MCLKI+(1ns+/-0.5ns).
This is shown in Figure 6-23.
duct(s) Low skew clock driver:
Obsolete Pro MCLKO
L+(1ns+/- 0.5ns)
DIMM CKn input
DIMM CKn input
DIMM CKn input
L+75mm*
STPC MCLKI
20pF
* No additional 75mm when SDRAM directly soldered on board
92/108
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