CS61880 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS61880 Datasheet PDF : 70 Pages
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CS61880
14.26 AWG Enable Register (19h)
BIT NAME
Description
The AWG enable register is used for selecting the source of the customized transmission
pulse-shape. Setting bit n to “1” in this register selects the AWG as the source of the output
[7:0] AWGN 7-0 pulse shape for channel n. When bit n is set to “0” the pre-programmed pulse shape in the
ROM is selected for transmission on channel n. (Refer to Arbitrary Waveform Generator
(See Section 15 on page 42). Register bits default to 00h after power-up or reset.
14.27 AWG Overflow Interrupt Enable Register (1Ah)
BIT
NAME
Description
This register enables changes in the overflow status to be reflected in the AWG Interrupt Sta-
[7:0] AWGE 7-0 tus register, thus causing as interrupt on the INT pin. Interrupts are maskable on a per-chan-
nel basis. Register bits default to 00h after power-up or reset.
14.28 AWG Overflow Interrupt Status Register (1Bh)
BIT
NAME
Description
The bits in this register indicate a change in status since the last AWG overflow interrupt. An
[7:0] AWGI 7-0 AWG overflow occurs when invalid phase data are entered, such that a sample-by-sample
addition of UI0 and UI1 results in values that exceed the arithmetic range of the 7-bit repre-
sentation. Reading this register clears the interrupt, which deactivates the INT pin. Register
bits default to 00h after power-up or reset.
14.29 Reserved Register (1Ch)
BIT
NAME
[7:0] RSVD 7-0
14.30 Reserved Register (1Dh)
Description
RESERVED
BIT
NAME
[7:0] RSVD 7-0
14.31 Bits Clock Enable Register (1Eh)
Description
RESERVED
BIT
NAME
Description
[7:0] BITS 7-0 Writing a “1” to bit n in this register changes channel n to a stand-alone timing recovery unit
used for G.703 clock recovery. (Refer to BUILDING INTEGRATED TIMING SYSTEMS
(BITS) CLOCK MODE (See Section 8 on page 23) for a better description of the G.703 clock
recovery function). Register bits default to 00h after power-up or reset.
14.32 Reserved Register (1Fh)
BIT
NAME
[7:0] RSVD 7-0
Description
RESERVED
40
DS450PP2
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