CS61880 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS61880

Octal E1 Line Interface Unit

Cirrus Logic 

CS61880

14.17 Line Length Channel ID Register (10h)

BIT

NAME

Description

[7:3] RSVD 7-3

RESERVED (These bits must be set to 0.)

The value written to these bits specify the LIU channel for which the Pulse Shape Configura-

tion Data (register 11h) applies. For example, writing a value of a binary 000 to the 3-LSBs

[2:0] LLID 2-0 will select channel 0. The pulse shape configuration data for the channel specified in this reg-

ister are written or read through the Line Length Data Register (11h). Register bits default

to 00h after power-up or reset.

14.18 Line Length Data Register (11h)

BIT

NAME

Description

The value written to the 4-LSBs of this register specifies whether the device is operating in

either E1 75Ω or E1 120Ω mode and the associated pulse shape as shown below is being

transmitted. Register bits default to 00h after power-up or reset.

[7:5] RSVD

RESERVED (These bits must be set to 0.)

This bit specifies the use of internal (Int_ExtB = 1) or external (Int_ExtB = 0) receiver line

[4] INT_EXTB matching. The line impedance for both the receiver and transmitter are chosen through the

LEN [3:0] bits in this register.

These bits set the line impedance for both the receiver and the transmitter path and the

[3:0] LEN[3:0] desired pulse shape for a specific channel. The channel is selected with the Line Length

Channel ID register (0x10). The following table shows the available transmitter pulse

shapes.

Table 12. Transmitter Pulse Shape Selection

LEN [3:0]

0000

1000

Operation

Mode

E1

E1

Line Length

Selection

120 Ω 3.0 V

75 Ω 2.37 V

Phase Samples

per UI

12

12

14.19 Output Disable Register (12h)

BIT

NAME

Description

[7:0] OENB 7-0 Setting bit n of this register to “1” High-Z the TX output driver on channel n of the device.

Register bits default to 00h after power-up or reset.

14.20 AIS Status Register (13h)

BIT

NAME

Description

[7:0] AISS 7-0 A “1” in bit position n indicates that the receiver has detected an AIS condition on channel n,

which generates an interrupt on the INT pin. Register bits default to 00h after power-up or

reset.

38

DS450PP2

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