CS493112-CL 查看數據表（PDF） - Cirrus Logic

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CS493112-CL

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

8. BOOT PROCEDURE & RESET

In this section the process of booting and

downloading to the CS493XX will be covered as

well as how to perform a soft reset. Host boot and

autoboot and reset are covered in this section.

8.1. Host Boot

A flow diagram of a typical serial download

sequence and a typical parallel download

sequence will be presented, as well as

pseudocode representing a download sequence

from the programmers perspective. The

pseudocode is written in a general sense where

function calls are made to Write_* and Read_*.

The * can be replaced by I2C or SPI for the serial

download sequence, and INTEL or MOTO for the

parallel download sequence, depending on the

mode of host communication. For each case the

general download algorithm is the same.

The download and boot procedure is

accomplished with RESET (pin 36), and the

communication pins discussed in Section 6,

“Control” on page 36. The flow diagrams in

Figure 33. Typical Serial Boot and Download

Procedure, and Figure 34. Typical Parallel Boot

and Download Procedure, illustrate typical boot

and download procedures. When reading in serial

mode, you must check that INTREQ is low to start

reading. Similarly, in parallel mode you must check

HOUTRDY.

Table 9 defines the boot write messages and

Table 10 defines the boot read messages in

mnemonic and actual hex value. These messages

will be used in the boot sequence.

Hardware configuration messages are used to

define the behavior of the DSP’s audio ports. A

more detailed description of the different hardware

configurations can be found in the Section 11,

“Hardware Configuration” on page 74.

The software configuration messages are specific

to each application. The application code user’s

guide for each application provides a list of all

pertinent configuration messages. Writing the

KICKSTART message to the CS493XX begins the

audio decode process. The KICKSTART message

will also be described in the user’s guide for each

application. Until the KICKSTART has been sent,

the decoder is in a wait state.

MNEMONIC

VALUE

SOFT_RESET

0x000001

RESERVED

0x000002

RESERVED

0x000003

DOWNLOAD_BOOT

0x000004

BOOT_SUCCESS_RECEIVED

0x000005

Table 9. Boot Write Messages

MNEMONIC

VALUE

BOOT_START

0x01

BOOT_SUCCESS

0x02

APPLICATION_FAILURE

0xF0

BOOT_ERROR

0xFA

INVALID_MSG

0xFB

BOOT_ERROR

0xFC

INIT_FAILURE

0xFD

INIT_FAILURE

0xFE

BAD_CHECKSUM

0xFF

Table 10. Boot Read Messages

8.1.1. Serial Download Sequence

The following is a detailed description of a serial

download sequence for the CS493XX.

Note: When reading from the chip in a serial

communication mode, the host must wait for the

interrupt request (INTREQ) to fall before

starting the read cycle.

1) A download sequence is started when the host

issues a hard reset and holds the mode pins

appropriately (WR, RD, and PSEL).

2) The host should then send the boot message

DOWNLOAD_BOOT (0x000004). This causes

the CS493XX to initialize itself for download.

3) If the initialization was successful the

CS493XX sends out the boot message

BOOT_START (0x01) and the host should

proceed to step 5.

4) If initialization fails, the CS493XX sends out an

INIT_FAILURE boot message byte (0xFD or

0xFE), INVALID_MSG byte (0xFB), or

BOOT_ERROR byte (0xFA or 0xFC) and spins

54

DS339F7

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