CS493112-CL 查看數據表（PDF） - Cirrus Logic

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CS493112-CL

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

Due to the internal, multiplexed design of the pins,

certain signals may or may not require termination

depending on the mode being used. If a parallel

host communication mode is not being used,

GPIO[11:0] must be terminated or driven as these

pins will come up as high impedance inputs and

will be prone to oscillation if they are left floating.

The specific termination requirements may vary

since the state of some of the GPIO pins will

determine the communication mode at the rising

edge of reset (please see Section 6, “Control” on

page 36 for more information). For the explicit

termination requirements of each communication

mode please see the typical connection diagrams.

Generally a 4.7k Ohm resistor is recommended for

open drain pins. The communication mode setting

pins (please see Section 6, “Control” on page 36

for more information) should also be terminated

with a 4.7k resistor. A 10k Ohm resistor is sufficient

for the GPIO pins and unused inputs.

3.3. Phase Locked Loop Filter

The internal phase locked loop (PLL) of the

CS493XX requires an external filter for successful

operation. The topology of this filter is shown in the

typical connection diagrams. The component

values are shown below. Care should be taken

when laying out the filter circuitry to minimize trace

lengths and to avoid any close routing of high

frequency signals. Any noise coupled on to the

filter circuit will be directly coupled into the PLL,

which could affect performance.

Reference Designator

C1

C2

C3

R1

Value

2.2uF

220pF

10nF

200k Ohm

Table 1. PLL Filter Component Values

28

DS339F7

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