CS493302 查看數據表（PDF） - Cirrus Logic
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CS493302 Datasheet PDF : 90 Pages
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CS49300 Family DSP
1.15. Switching Characteristics — Digital Audio Output
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Parameter
Symbol
Min
MCLK period
(Note 1) Tmclk
40
MCLK duty cycle
(Note 1)
40
SCLK period for Master or Slave mode
(Note 2) Tsclk
40
SCLK duty cycle for Master or Slave mode
(Note 2)
45
Master Mode
(Note 2, 3)
SCLK delay from MCLK rising edge, MCLK as an input
Tsdmi
SCLK delay from MCLK rising edge, MCLK as an output
Tsdmo
–5
LRCLK delay from SCLK transition
(Note 4) Tlrds
AUDATA2–0 delay from SCLK transition
(Note 4) Tadsm
Slave Mode
(Note 5)
Time from active edge of SCLKN1(2) to LRCLKN1(2) transition
Tstlr
10
Time from LRCLKN1(2) transition to SCLKN1(2) active edge
Tlrts
10
AUDATA2–0 delay from SCLK transition
(Note 4, 6) Tadss
Max
Unit
-
ns
60
%
-
ns
55
%
15
ns
10
ns
10
ns
10
ns
-
ns
-
ns
15
ns
Notes: 1. MCLK can be an input or an output. These specifications apply for both cases.
2. Master mode timing specifications are characterized, not production tested.
3. Master mode is defined as the CS493XX driving both SCLK and LRCLK. When MCLK is an input, it is
divided to produce SCLK and LRCLK.
4. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the
point at which the data is valid.
5. Slave mode is defined as SCLK and LRCLK being driven by an external source.
6. This specification is characterized, not production tested.
22
DS339F7
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