STM32WB55VCY6TR 查看數據表（PDF） - STMicroelectronics
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STM32WB55VCY6TR
STMicroelectronics
STM32WB55VCY6TR Datasheet PDF : 193 Pages
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Electrical characteristics
STM32WB55xx STM32WB35xx
High
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
Figure 33. SPI timing diagram - master mode
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
tsu(MI)
MOSI
OUTPU T
tw(SCKH)
tw(SCKL)
MSB IN
th(MI)
MSB OUT
tv(MO)
BIT6 IN
B I T1 OUT
th(MO)
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.
tr(SCK)
tf(SCK)
LSB IN
LSB OUT
ai14136c
162/193
DS11929 Rev 10
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