S24163S2.7 查看數據表（PDF） - Summit Microelectronics

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S24163S2.7

Precision RESET Controller with 16K I2C Memory

Summit Microelectronics 

S24163

SDA

SCL

Master

Transmitter/

Receiver

VCC

RESET

Slave

Receiver

Slave

Transmitter/

Receiver

(24163)

Master

Transmitter

FIGURE 1. TYPICAL SYSTEM CONFIGURATION

Master

Transmitter/

Receiver

(µC/ µP)

2014 T fig01 2.0

SCL

SDA In

Data must

remain stable

while clock

is HIGH.

Change

of data

allowed

Data must

remain stable

while clock

is HIGH.

tHD:DAT

tSU:DAT

FIGURE 2. INPUT DATA PROTOCOL

tHD:DAT

2014 ILL4 1.0

SCL

SDA In

START

Condition

STOP

Condition

FIGURE 3. START AND STOP CONDITIONS

3

2014 ILL5 1.0

2014 2.0 3/21/00

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