CRD8900-1 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CRD8900-1

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Bus Interface Register:

EEPROM Command (Read/Write)

F-B

A

Reserved

ELSEL

Address: PacketPage base + 0040h

9

8

7-0

OB1

OB0

ADD7 to ADD0

This register is used to control the reading, writing and erasing of the EEPROM. See Section 3.5.

BIT NAME

DESCRIPTION

7-0 ADD7-

ADD0

Address of the EEPROM word being accessed.

9-8 OB1,OB0 Indicates the Opcode of the command being executed. See Table 3.7.

A

ELSEL

External logic select: When clear, the EECS pin is used to select the EEPROM. When

set, the ELCS pin is used to select the external LA decode circuit..

F-B Reserved Reserved and must be written as 0.

This register’s initial state after reset is: XXXX XXXX XXXX XXXX

Bus Interface Register:

EEPROM Data (Read/Write)

Address 0043h

Most-significant byte of EEPROM data.

Address: PacketPage base + 0042h

Address 0042h

Least-significant byte of the EEPROM data.

This register contains the word being written to, or read from, the EEPROM. See Section 3.5.

This register’s initial state after reset is: XXXX XXXX XXXX XXXX

Bus Interface Register:

Receive Frame Byte Counter (Read/only)

Address 0051h

Most-significant byte of byte count.

Address: PacketPage base + 0050h

Address 0050h

Least-significant byte of the byte count.

This register contains the count of the total number bytes received in the the current received frame. This count

continuously increments as more bytes in this frame are received. See Section 5.2.9.

This register’s initial state after reset is: XXXX XXXX XXXX XXXX

DS150PP2

43

Share Link: