CS8900-CQ 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Upon exit, there is a chip-wide reset (see Section

3.7 for more information about SW Suspend).

3.3.2 Allowing Time for Reset Operation

After a reset, the CS8900 goes through a self

configuration. This includes calibrating on-chip

analog circuitry, and reading EEPROM for valid-

ity and configuration. Time required for the reset

calibration is typically 10 ms. Software drivers

should not access registers internal to the

CS8900 during this time. When calibration is

done, bit INITD in the Self Status Register (reg-

ister 16) is set indicating that initialization is

complete, and the SIBUSY bit in the same regis-

ter is cleared indicating the EEPROM is no

longer being read or programmed.

3.3.3 Bus Reset Considerations

The CS8900 reads 3000h from IObase+0Ah af-

ter the reset, until the software writes a non-zero

value at IObase+0Ah. The 3000h address can be

used as part of the CS8900 signature when the

system scans for the CS8900. See Section 4.10,

I/O Space Operation.

After a reset, the ISA bus outputs INTRx and

DMARQx are tri-stated, thus avoiding any inter-

rupt or DMA channel conflicts on the ISA bus at

power-up time.

Initialization

After each reset (except EEPROM Reset), the

CS8900 checks the sense of the EEDataIn pin to

see if an external EEPROM is present. If EEDI

is high, an EEPROM is present and the CS8900

automatically loads the configuration data stored

in the EEPROM into its internal registers (see

next section). If EEDI is low, an EEPROM is not

present and the CS8900 comes out of reset with

the default configuration shown in Table 3.3.

A low-cost serial EEPROM can be used to store

configuration information that is automatically

16

PacketPage

Address

Register

Contents

Register

Description

0020h

0300h

I/O Base Address*

0022h

XXXX XXXX

XXXX X100

Interrupt Number

0024h

XXXX XXXX

XXXX XX11

DMA Channel

0026h

0000h

DMA Start of Frame

Offset

0028h

X000h

DMA Frame Count

002Ah

0000h

DMA Byte Count

002Ch

XXX0 0000h Memory Base Address

0030h

XXX0 0000h

Boot PROM Base

Address

0034h

XXX0 0000h

Boot PROM Address

Mask

0102h

0003h

Register 3 - RxCFG

0104h

0005h

Register 5 - RxCTL

0106h

0007h

Register 7 - TxCFG

0108h

0009h

Register 9 - TxCMD

010Ah

000Bh

Register B - BufCFG

010Ch

Undefined

Reserved

010Eh

Undefined

Reserved

0110h

Undefined

Reserved

0112h

0013h

Register 13 - LineCTL

0114h

0015h

Register 15 - SelfCTL

0116h

0017h

Register 17 - BusCTL

0118h

0019h

Register 19 - TestCTL

* I/O base address is unaffected by Software

Suspend mode.

Table 3.3. Default Configuration

EEPROM Type

’C46 (non-sequential)

’CS46 (sequential)

’C56 (non-sequential)

’CS56 (sequential)

’C66 (non-sequential)

’CS66 (sequential)

Size (16-bit words)

64

64

128

128

256

256

Table 3.4. Supported EEPROM Types

DS150PP2

Share Link: