CS4812 查看數據表（PDF） - Cirrus Logic
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CS4812 Datasheet PDF : 36 Pages
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CS4812
PROM memory mapping is handled automatically
by the development tools and is transparent to the
designer.
3.5.2.2 I2C Slave Mode
In I2C slave mode, a write sequence from an exter-
nal host controller is shown in Figure 22.. The host
controller sends a write preamble consisting of a
start condition followed by the slave address for the
CS4812. The slave address byte consists of a 7-bit
address field (00100|AD1|AD0) followed by a
Read/Write bit (set to 0). AD1 and AD0 correspond
to the logic levels applied to the these pins on the
CS4812. The host controller then sends a MAP
byte which contains the address of the control reg-
ister to be accessed followed by the actual data byte
to be written to the register designated by the MAP.
Upon completion of this, the host controller then
sends a stop condition to complete the transaction.
Figure 21 shows the I2C slave mode write flow di-
agram
In I2C slave mode, a read sequence by an external
host controller is shown in Figure 23. The host con-
troller sends a write preamble to the CS4812 which
SEND I2C START
WRITE ADDRESS BYTE
WITH R/W BIT = 0
GET ACK
SEND MAP BYTE
GET ACK
SEND DATABYTE
GET ACK
Y
MORE DATA?
N
SEND I2C STOP
Figure 21. I2C Slave Mode Write Flow Diagram
SCL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
SDA
0 0 1 0 0 AD1 AD0 0
INCR 6 5 4 3 2 1 0
76
ACK
ACK
10
76
ACK
10
START
Figure 22. Control Port Timing, I2C Slave Mode Write
DATA +n
76 10
ACK
STOP
SCL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CHIP ADDRESS (WRITE)
SDA
0 0 1 0 0 AD1 AD0 0
INCR 6
START
ACK
MAP BYTE
CHIP ADDRESS (READ)
DATA
DATA +1
5 4 3210
0 0 1 0 0 AD1 AD0 1
70
70
ACK
START
ACK
ACK
DATA + n
70
NO
ACK STOP
REQ
Figure 23. Control Port Timing, I2C Slave Mode Read
24
DS291PP3
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