CS4353(2009) 查看數據表（PDF） - Cirrus Logic

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CS4353
(Rev.:2009)

3.3 V Stereo Audio DAC with 2 VRMS Line Output

Cirrus Logic 

USER: Apply Power

Reset State

Outputs Grounded

USER: RESET Set High

or

RESET Tied High (if using POR)

Power-Down State

USER: Apply MCLK

Initialization State

USER: Apply LRCK and SCLK

MCLK/LRCK Ratio Detection

USER: Change MCLK/LRCK ratio

Valid MCLK/LRCK Ratio

Power-Up State

Outputs Muted

CS4353

USER: RESET

Set Low

or

Remove MCLK

Valid MCLK/LRCK Ratio

Normal Operation State

Analog Output Generated

USER: Change MCLK/LRCK ratio

Mute State

Figure 9. Initialization and Power-down Sequence Diagram

18

DS803F1

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