AT89C51CC03C-RLTIM 查看數據表（PDF） - Atmel Corporation
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AT89C51CC03C-RLTIM Datasheet PDF : 197 Pages
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AT89C51CC03
Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the
WDT duration.
Table 42. Machine Cycle Count
S2
S1
S0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Machine Cycle Count
214
215
216
217
218
219
220
221
To compute WD Time-Out, the following formula is applied:
Note:
FTime Out F –
WDX X osc Svalue =
----------------------------------------------------------------------------
6 × 2 2 ∧ 2(214 × 2
)
Svalue represents the decimal value of (S2 S1 S0)
The following table outlines the time-out value for FoscXTAL = 12 MHz in X1 mode
Table 43. Time-Out Computation
S2
S1
S0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Fosc = 12 MHz
16.38 ms
32.77 ms
65.54 ms
131.07 ms
262.14 ms
524.29 ms
1.05 s
2.10 s
Fosc = 16 MHz
12.28 ms
24.57 ms
49.14 ms
98.28 ms
196.56 ms
393.12 ms
786.24 ms
1.57 s
Fosc = 20 MHz
9.82 ms
19.66 ms
39.32 ms
78.64 ms
157.28 ms
314.56 ms
629.12 ms
1.25 s
83
4182K–CAN–05/06
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