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AT89C51CC03C-RLTIM 查看數據表(PDF) - Atmel Corporation

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AT89C51CC03C-RLTIM
Atmel
Atmel Corporation 
AT89C51CC03C-RLTIM Datasheet PDF : 197 Pages
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AT89C51CC03
Figure 22. External Code Fetch Waveforms
CPU Clock
ALE
PSEN#
P0 D7:0
PCL
P2 PCH
D7:0
PCH
PCL
D7:0
PCH
Flash Memory
Architecture
AT89C51CC03 features two on-chip Flash memories:
• Flash memory FM0:
containing 64K Bytes of program memory (user space) organized into 128 byte
pages,
• Flash memory FM1:
2K Bytes for boot loader and Application Programming Interfaces (API).
The FM0 can be program by both parallel programming and Serial In-System Program-
ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP
mode is detailed in the "In-System Programming" section.
All Read/Write access operations on Flash Memory by user application are managed by
a set of API described in the "In-System Programming" section.
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Figure
23 and Figure 24 show the Flash memory configuration with ENBOOT=1 and
ENBOOT=0.
Figure 23. Flash Memory Architecture with ENBOOT=1 (boot mode)
Hardware Security (1 byte)
Extra Row (128 Bytes)
Column Latches (128 Bytes)
FFFFh
64K Bytes
F800h
FM0
0000h
2K Bytes
Flash memory
boot space
FM1
FFFFh
F800h
FM1 mapped between FFFFh and
F800h when bit ENBOOT is set in
AUXR1 register
Memory space not accessible
43
4182K–CAN–05/06

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