QL82SD-5PB516M 查看數據表（PDF） - QuickLogic Corporation
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QL82SD-5PB516M Datasheet PDF : 60 Pages
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QL82SD Device Data Sheet Rev C
QS
A1
A2
A3
A4
AZ
A5
A6
OS
OP
B1
B2
C1
OZ
C2
MP
MS
QZ
D1
D2
E1
E2
NP
NZ
NS
Q2Z
F1
F2
F3
F4
FZ
F5
F6
PS
PP
QC
QR
Figure 45: SERDES Logic Cell
RAM Block Description
General Description
The QuickSD device includes multiple dual-port 2,304-bit RAM modules for implementing
RAM and FIFO functions. Each module is user-configurable into four different block
organizations. Modules can also be cascaded horizontally to increase their effective width or
vertically to increase their effective depth as shown in the following figure. The RAM can also
be configured as a modified Harvard Architecture, similar to those found in DSPs.
2,304-bit Module
MODE [1:0] ASYNCRD
WA [9:0]
RA [9:0]
WD [17:0] RD [17:0]
WE
RE
WCLK
RCLK
Figure 46: SERDES 2,304-bit RAM Module
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Preliminary
© 2002 QuickLogic Corporation
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