M34D64-WMN6 查看數據表（PDF） - STMicroelectronics

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M34D64-WMN6

64 Kbit serial I²C bus EEPROM with hardware write control on top quarter of memory

STMicroelectronics 

M34D64-W

Figure 6. I2C bus protocol

Signal description

SCL

SDA

Start

condition

SDA

Input

SDA

Change

Stop

condition

SCL

SDA

1

2

3

MSB

Start

condition

7

8

9

ACK

SCL

1

2

3

7

8

9

SDA

MSB

ACK

Stop

condition

AI00792c

Table 2.

Device select code

Device type identifier(1)

Chip Enable address(2)

RW

b7

b6

b5

b4

b3

b2

b1

b0

Device select

code

1

0

1

0

E2

E1

E0

RW

1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 are compared against the respective external pins on the memory device.

Table 3. Most significant byte

b15

b14

b13

b12

b11

b10

b9

b8

Table 4. Least significant byte

b7

b6

b5

b4

b3

b2

b1

b0

11/27

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