C8051F524-C-IM 查看數據表（PDF） - Silicon Laboratories

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C8051F524-C-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

SFR Definition 8.1. SP: Stack Pointer

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x81

Bits7–0: SP: Stack Pointer.

The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented

before every PUSH operation. The SP register defaults to 0x07 after reset.

SFR Definition 8.2. DPL: Data Pointer Low Byte

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x82

Bits7–0: DPL: Data Pointer Low.

The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly

addressed XRAM and Flash memory.

SFR Definition 8.3. DPH: Data Pointer High Byte

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x83

Bits7–0: DPH: Data Pointer High.

The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly

addressed XRAM and Flash memory.

Rev. 1.4

87

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