C8051F521-C-IM 查看數據表（PDF） - Silicon Laboratories

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C8051F521-C-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

Note that false rising edges and falling edges can be detected when the comparator is first powered-on or

if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the

rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is

enabled or its mode bits have been changed. This Power Up Time is specified in Table 2.7 on page 31.

SFR Definition 7.1. CPT0CN: Comparator0 Control

R/W

CP0EN

Bit7

R

CP0OUT

Bit6

R/W

CP0RIF

Bit5

R/W

CP0FIF

Bit4

R/W

R/W

R/W

R/W

Reset Value

CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000

Bit3

Bit2

Bit1

Bit0 SFR Address:

0x9B

Bit7: CP0EN: Comparator0 Enable Bit.

0: Comparator0 Disabled.

1: Comparator0 Enabled.

Bit6: CP0OUT: Comparator0 Output State Flag.

0: Voltage on CP0+ < CP0–.

1: Voltage on CP0+ > CP0–.

Bit5: CP0RIF: Comparator0 Rising-Edge Flag.

0: No Comparator0 Rising Edge has occurred since this flag was last cleared.

1: Comparator0 Rising Edge has occurred.

Bit4: CP0FIF: Comparator0 Falling-Edge Flag.

0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.

1: Comparator0 Falling-Edge has occurred.

Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.

00: Positive Hysteresis Disabled.

01: Positive Hysteresis = 5 mV.

10: Positive Hysteresis = 10 mV.

11: Positive Hysteresis = 20 mV.

Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.

00: Negative Hysteresis Disabled.

01: Negative Hysteresis = 5 mV.

10: Negative Hysteresis = 10 mV.

11: Negative Hysteresis = 20 mV.

78

Rev. 1.4

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