C8051F524-C-IM 查看數據表（PDF） - Silicon Laboratories

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C8051F524-C-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

Table 3.9. QFN-20 Landing Diagram Dimensions

Symbol

Min

Max

C1

3.90

4.00

C2

3.90

4.00

E

0.50 BSC.

X1

0.20

0.30

X2

2.75

2.85

Y1

0.65

0.75

Y2

2.75

2.85

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise

noted.

2. This land pattern design is based on the IPC-7351 guidelines.

Solder Mask Design

3. All metal pads are to be non-solder mask defined (NSMD).

Clearance between the solder mask and the metal pad is to be

60 µm minimum, all the way around the pad.

Stencil Design

4. A stainless steel, laser-cut and electro-polished stencil with

trapezoidal walls should be used to assure good solder paste

release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size should be 1:1 for all

perimeter pads.

7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be

used for the center ground pad.

Card Assembly

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-

020 specification for Small Body Components.

Rev. 1.4

51

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