C8051F521-C-IM 查看數據表（PDF） - Silicon Laboratories
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C8051F521-C-IM Datasheet PDF : 221 Pages
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C8051F52x/F53x
Table 3.1. Pin Definitions for the C8051F52x and C8051F52xA (DFN 10)
Name Pin Numbers Type Description
RST/
C2CK
‘F52xA ‘F52x
‘F52x-C
1
1
D I/O
D I/O
Device Reset. Open-drain output of internal POR or VDD monitor.
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
reset, as defined in Table 2.8 on page 32. A 1 k pullup to VRE-
GIN is recommended. See Reset Sources Section for a complete
description.
P0.0/
Clock signal for the C2 Debug Interface.
2
2 D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
VREF
A O or External VREF Input. See VREF Section.
D In
GND
3
3
Ground.
VDD
4
4
Core Supply Voltage.
VREGIN
5
5
On-Chip Voltage Regulator Input.
P0.5/RX*/ 6
— D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
CNVSTR
P0.5/
—
D In External Converter start input for the ADC0, see Section “4. 12-
Bit ADC (ADC0)” on page 52 for a complete description.
6 D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
CNVSTR
D In External Converter start input for the ADC0, see Section “4. 12-
Bit ADC (ADC0)” on page 52 for a complete description.
P0.4/TX*
7
— D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
P0.4/RX* —
7 D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
P0.3
8
— D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
XTAL2
D I/O
External Clock Output. For an external crystal or resonator, this
pin is the excitation driver. This pin is the external clock input for
CMOS, capacitor, or RC oscillator configurations. See Section
“14. Oscillators” on page 135.
Note: Please refer to Section “20. Device Specific Behavior” on page 210.
36
Rev. 1.4
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