C8051F524-C-IM 查看數據表（PDF） - Silicon Laboratories

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C8051F524-C-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

Revision 1.2 to 1.3

 Updated “System Overview” on page 13 with a voltage range specification for the internal oscillator.

 Updated Table 2.11 on page 34 with new conditions for the internal oscillator accuracy. The internal

oscillator accuracy is dependent on the operating voltage range.

 Updated Section 2 to remove the internal oscillator curve across temperature diagram.

 Updated Figure “4.5 12-Bit ADC Burst Mode Example with Repeat Count Set to 4” on page 58 with new

timing diagram when using CNVSTR pin.

 Updated SFR Definition 5.1 (REF0CN) with oscillator suspend requirement for ZTCEN.

 Updated SFR Definition 6.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and

must be written to 1b.

 Updated Section “8.3.3. Suspend Mode” on page 90 with note regarding ZTCEN.

 Updated Section “17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A)” on page 164 with

a voltage range specification for the internal oscillator.

Revision 1.3 to 1.4

 Added ‘AEC-Q100’ qualification information on page 1.

 Changed page headers throughout the document from ‘C8051F52x/F52xA/F53x/F53xA’ to

‘C8051F52x/53x’.

 Updated supply voltage to "2.0 to 5.25 V" on page 1 and in Section 1 on page 13.

 Corrected reference to development kit (C8051F530DK) in Section “1.2.4. On-Chip Debug Circuitry” on

page 18.

 Updated minimum Supply Input Voltage (VREGIN) for C8051F52x-C/F53x-C devices in Table 2.2 on

page 26 and Table 2.6 on page 30.

 Updated digital supply current (IDD and Idle IDD) typical values for condition ‘Clock = 25 MHz’ in

Table 2.2 on page 26.

 Updated IDD Frequency Sensitivity and Idle IDD Frequency Sensitivity values in Table 2.2 on page 26;

removed Figure 2.1 and Figure 2.2 that used to provide the same frequency sensitivity slopes. Also

removed IDD Supply Sensitivity and Idle IDD Supply Sensitivity typical values.

 Added Digital Supply Current (Stop or Suspend Mode) values at multiple temperatures Table 2.2 on

page 26.

 Added a note in Table 2.3, “ADC0 Electrical Characteristics,” on page 28 with reference to Section

“4.4. Selectable Gain” on page 60; also added note to indicate that additional tracking time may be

necessary if VDD is less than the minimum specified VDD.

 Split off temperature sensor specifications from Table 2.3 into a separate table Table 2.4; Updated

temperature sensor gain and added supply current values.

 Added temperature condition for Bias Current specification in Table 2.6 on page 30.

 Updated Comparator Input Offset Voltage values in Table 2.7 on page 31.

 Updated VDD Monitor (VDDMON0) Low Threshold (VRST-LOW) minimum value for C8051F52xA/F52x-

C/F53xA/F53x-C devices in Table 2.8 on page 32.

 Updated VDD Monitor (VDDMON0) supply current values in Table 2.8 on page 32.

 Added specifications for the new level-sensitive VDD monitor (VDDMON1) to Table 2.8, “Reset

Electrical Characteristics,” on page 32 and also added notes to clarify the applicable VRST theshold

level.

 Added note in Table 2.9, “Flash Electrical Characteristics,” on page 33 to describe the minimum flash

programming temperature for –I (Industrial Grade) devices; Also added the same note and references

to it in Section “12.1. Programming The Flash Memory” on page 113, Section “12.3. Non-volatile Data

Storage” on page 117, and in SFR Definition 12.1 (PSCTL).

218

Rev. 1.4

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