C8051F521-C-IM 查看數據表（PDF） - Silicon Laboratories

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C8051F521-C-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

SFR Definition 13.5. P0MDOUT: Port0 Output Mode

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xA4

Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis-

ter P0MDIN is logic 0.

0: Corresponding P0.n Output is open-drain.

1: Corresponding P0.n Output is push-pull.

Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT.

SFR Definition 13.6. P0SKIP: Port0 Skip

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xD4

Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits.

These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-

log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-

lator circuit, CNVSTR input) should be skipped by the Crossbar.

0: Corresponding P0.n pin is not skipped by the Crossbar.

1: Corresponding P0.n pin is skipped by the Crossbar.

130

Rev. 1.4

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