CS5376-BS 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

sampling instant, digital filter phase, and test bit-

stream phase to ensure measurement timing is con-

sistent across the network.

Time Break Controller

The CS5376 time break controller places a timing

reference flag in the status bits of the digital filter

output word. This timing reference flag is used to

mark measurement events in the digital data, or as

a digital sync to align multiple data streams during

post-processing. An externally generated TIMEB

signal starts a programmable sample counter (used

to correct for digital filter group delay), and when

it expires the time break flag is set in the next out-

put data word.

2.4 Register Descriptions

Decimation Engine Registers

Hardware functions and digital filter settings in the

CS5376 are controlled by registers in the decima-

tion engine. A summary of decimation engine reg-

isters is shown in Figure 6 on page 12. See

“Decimation Engine Registers” on page 99 for a

detailed listing of all decimation engine register bit

settings.

SPI 1 Registers

Decimation engine registers are not directly acces-

sible to the communication interface. Instead, they

are indirectly read and written using SPI 1 regis-

ters. See “Serial Peripheral Interface 1” on page 21

for a description of how to use the SPI 1 port to ac-

cess decimation engine registers.

Each 24-bit SPI 1 register is divided into three 8-bit

registers consisting of a high, mid, and low byte. A

summary of SPI 1 registers is shown in Figure 6 on

page 12. See “SPI 1 Registers” on page 94 for a de-

tailed listing of all SPI 1 register bit settings.

DS256PP1

11

Share Link: