CS42438-DMZR 查看數據表（PDF） - Cirrus Logic

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CS42438-DMZR

108 dB, 192 kHz 6-in, 8-out TDM CODEC

Cirrus Logic 

7 REGISTER DESCRIPTION

All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which

are read only. See the following bit definition tables for bit assignment information. The default state of

each bit after a power-up sequence or reset is listed in each bit description.

7.1 MEMORY ADDRESS POINTER (MAP)

Not a register

7

INCR

6

MAP6

5

MAP5

4

MAP4

3

MAP3

2

MAP2

1

MAP1

0

MAP0

7.1.1 INCREMENT(INCR)

Default = 1

Function:

Memory address pointer auto increment control

0 - MAP is not incremented automatically.

1 - Internal MAP is automatically incremented after each read or write.

7.1.2 MEMORY ADDRESS POINTER (MAP[6:0])

Default = 0000001

Function:

Memory address pointer (MAP). Sets the register address that will be read or written by the control

port.

7.2 CHIP I.D. AND REVISION REGISTER (ADDRESS 01H) (READ ONLY)

7

Chip_ID3

6

Chip_ID2

5

Chip_ID1

4

Chip_ID0

3

Rev_ID3

2

Rev_ID2

1

Rev_ID1

7.2.1 CHIP I.D. (CHIP_ID[3:0])

Default = 0000

Function:

I.D. code for the CS42438. Permanently set to 0000.

7.2.2 CHIP REVISION (REV_ID[3:0])

Default = 0001

Function:

CS42438 revision level. Revision A is coded as 0001.

0

Rev_ID0

42

DS646PP2

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