CS42438-DMZR 查看數據表（PDF） - Cirrus Logic

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CS42438-DMZR

108 dB, 192 kHz 6-in, 8-out TDM CODEC

Cirrus Logic 

5.3 Analog Outputs

5.3.1 Initialization

The initialization and Power-Down sequence flow chart is shown in Figure 11 on page 31. The

CS42438 enters a Power-Down state upon initial power-up. The interpolation & decimation fil-

ters, delta-sigma modulators and control port registers are reset. The internal voltage reference,

multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass fil-

ters are powered down.

The device will remain in the Power-Down state until the RST pin is brought high. The control

port is accessible once RST is high and the desired register settings can be loaded per the in-

terface descriptions in the “Control Port Description and Timing” on page 36. In hardware mode

operation, the hardware mode pins must be setup before RST is brought high. All features will

default to the hardware mode defaults as listed in Table 2.

Once MCLK is valid, VQ will quickly charge to VA/2, and the internal voltage reference, FILT+,

will begin powering up to normal operation. Power is applied to the D/A converters and switched-

capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is

valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK fre-

quency ratio. After an approximate 2000 sample period delay, normal operation begins.

5.3.2 Line-level Outputs and Filtering

The CS42438 contains on-chip buffer amplifiers capable of producing line level differential as

well as single-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC

level of approximately VQ.

The delta-sigma conversion process produces high frequency noise beyond the audio pass-

band, most of which is removed by the on-chip analog filters. The remaining out-of-band noise

can be attenuated using an off-chip low pass filter.

See “DAC Output Filter” on page 54 for recommended output filter. The active filter configuration

accounts for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins.

Also shown is a passive filter configuration which minimizes costs and the number of compo-

nents.

Figure 12 shows the full-scale analog output levels. All outputs are internally biased to VQ, ap-

proximately VA/2.

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DS646PP2

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