CS5501 查看數據表（PDF） - Cirrus Logic

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CS5501

Non-aliasing, 16- & 20-bit A/D Converters

Cirrus Logic 

CDB5501 CDB5503

CDB5501/CDB5503

SDATA (fig. 2)

V+

MC145406

14 U11A 3

RN 1.5

DRDY (fig. 2)

47 k 12 U11B

5

P6

DATA 3

CTS

5

10 U11C 7

DSR 6

DCD 8

13 U11D 4 RTS 4

11 U11E 6

DTR 20

V+

0.1 µF

1

15

16

U11F

2

9

V-

8

0.1 µF

Figure 4. RS-232 Port

7

NC

1

Sub-D

25 pin

addition, an appropriate baud clock needs to be

input to the CS5501. See AC (Asynchronous

Communication) mode mentioned earlier for an

explanation of the baud rate clock generator and

the data format of the output data in the AC

mode.

The DRDY output from the CS5501 signals the

CTS (Clear To Send) line of the RS-232 interface

when data is available. The Decimation Counter

can be used to determine how frequently output

data is to be transmitted.

The RS-232 interface on the evaluation card is

functionally adequate but it is not compliant with

the EIA RS-232 standard. When the MC145406

RS-232 receiver/driver chip is operated off of ± 5

volt supplies rather than ± 6 volts (see the

MC145406 data sheet for details) its driver output

swing is reduced below the EIA specified limits.

In practical applications this signal swing limita-

tion only reduces the length of cable the circuit is

capable of driving.

DS31DB43

DECIMATION COUNTER

Each time a data word is available for output

from the CS5501/CS5503, the DRDY line goes

low, provided the output port was previously

emptied. If the DRDY line is directly tied to the

CS input of the CS5501/CS5503, the converter

will output data every time a data word is pre-

sented to the output pin. In some applications it is

desirable to reduce the output word rate. The rate

Decimation Counter Accumulates 2n+1 DRDY Pulses Before CS is

Enabled.

P-4

2n+1

0

2

1

4

2

8

3

16

4

32

5

64

6

128

7

256

8

512

9

1024

10

2048

11

4096

P-9

DC Output to CS

NC

No Connection

DC

Decimation Counter

Table 4. Decimation Counter Control

can be reduced by lowering the rate at which the

CS line to the chip is enabled. The

CDB5501/CDB5503 evaluation board uses a

counter, IC U3 for this purpose. It is known as a

decimation counter (see Figure 2). The outputs of

the counter are available at connector P4. The

counter accumulates 2n+1 counts (n = 0, 2, …11)

at which time the selected output enables the CS

input to the CS5501/CS5503 (if the jumper in P9

is in the DC, Decimation Counter, position). The

49

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