CS5501 查看數據表（PDF） - Cirrus Logic

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CS5501

Non-aliasing, 16- & 20-bit A/D Converters

Cirrus Logic 

CS5501 CS5503

CS5501/CS5503

Filtering

At the system level, the digital filter in the

CS5501/CS5503 can be modeled exactly like

an analog filter with a few minor differences.

Digital filtering resides behind the A/D conver-

sion and can thus reject noise injected during

the conversion process (i.e. power supply rip-

ple, voltage reference noise, or noise in the

ADC itself). Analog filtering cannot.

Also, since digital filtering resides behind the

A/D converter, noise riding unfiltered on a

near-full-scale input could potentially over-

range the ADC. In contrast, analog filtering

removes the noise before it ever reaches the

converter. To address this issue, the

CS5501/CS5503 each contain an analog modu-

lator and digital filter which reserve headroom

such that the device can process signals with

100mV "excursions" above full-scale and still

output accurately converted and filtered data.

Filtered input signals above full-scale still result

in an output of all ones.

The digital filter’s corner frequency occurs at

CLKIN/409,600, where CLKIN is the master

clock frequency. With a 4.096MHz clock, the

filter corner is at 10Hz and the output register is

updated at a 4kHz rate. CLKIN frequency can be

reduced with a proportional reduction in the filter

corner frequency and in the update rate to the out-

put register. A plot of the filter response is shown

in the specification tables section of this data

sheet.

Both the CS5501/CS5503 employ internal digi-

tal filtering which creates a 6-pole Gaussian

relationship. With the corner frequency set at

10Hz for minimized settling time, the

CS5501/CS5503 offer approximately 55dB re-

jection at 60Hz to signals coming into either

the AIN or VREF pins. With a 5Hz cut-off,

60Hz rejection increases to more than 90dB.

The digital filter (rather than the analog modula-

tor) dominates the converters’ settling for

step-function inputs. Figure 13 illustrates the set-

tling characteristics of the filter. The vertical axis

is normalized to the input step size. The horizon-

tal axis is in filter cycles. With a full scale input

step (2.5 V in unipolar mode) the output will ex-

hibit an overshoot of about 0.25 LSB16 in the

CS5501 and 4 LSB20 in the CS5503.

1.1

1.0 Vertical scale normalized

to input step size

0.9

0.8

0.7

See (b) for

expanded view

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0

50 100 150 200 250 300 350 400 450 500

Filter Cycles (1024 CLKIN cycles)

(a) Settling Time Due to Input Step Change

1.0000125

1.0000100

1.0000075

1.0000050

1.0000025

1.0000000

1.00000381

Vertical scale normalized

to input step size

0.9999975

0.9999950

0.9999925

0.9999900

0.99999850

Settling response is monotonically

increasing from zero to here, and

then exhibits one overshoot and

one undershoot as shown.

0.9999875

500 530 560 590 620 650 680 710 740

Filter Cycles (1024 CLKIN cycles)

(b) Expanded Version of (a)

DS31F54

23

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