PSD854F3VA-90UT 查看數據表（PDF） - STMicroelectronics

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PSD854F3VA-90UT

Flash in-system programmable (ISP) ipherals for 8-bit MCUs, 5 V

STMicroelectronics 

PLDS

PSD8XXFX

14.2 Decode PLD (DPLD)

The DPLD, shown in Figure 13, is used for decoding the address for internal and external

components. The DPLD can be used to generate the following decode signals:

● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms

each)

● 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three

product terms each)

● 1 internal SRAM Select (RS0) signal (two product terms)

● 1 internal CSIOP Select (PSD Configuration register) signal

● 1 JTAG Select signal (enables JTAG on port C)

● 2 internal Peripheral Select signals

) (Peripheral I/O mode).

t(s Figure 13. DPLD logic array

olete Produc I/O PORTS (PORT A,B,C)

(INPUTS)

(24)

bs MCELLAB.FB [7:0] (FEEDBACKS)

(8)

O MCELLBC.FB [7:0] (FEEDBACKS)

(8)

) - PGR0 -PGR7

(8)

t(s A[15:0] *

(16)

uc PD[2:0] (ALE,CLKIN,CSI)

(3)

d PDN (APD OUTPUT)

(1)

ro CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (3)

te P RESET

(1)

Obsole RD_BSY

(1)

3

CSBOOT 0

3

CSBOOT 1

3

CSBOOT 2

3

CSBOOT 3

3

FS0

3

FS1

3

FS2

3

FS3

8 PRIMARY FLASH

3

MEMORY SECTOR SELECTS

FS4

3

FS5

3

FS6

3

FS7

2

RS0

SRAM SELECT

1

CSIOP

I/O DECODER

SELECT

1

PSEL0

PERIPHERAL I/O MODE

1

PSEL1

SELECT

1

JTAGSEL

AI02873D

50/128

Doc ID 7833 Rev 7

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