
16-BIT TIMER (Cont’d)
Figure 27. Input Capture Block Diagram
ICAP1
pin
EDGE DETECT EDGE DETECT
ICIE
ICAP2
CIRCUIT2
CIRCUIT1
pin
IC2R Register
IC1R Register
ICF1
16-BIT
16-BIT FREE RUNNING
COUNTER
ST7263
(Control Register 1) CR1
IEDG1
(Status Register) SR
ICF2
0
0
0
(Control Register 2) CR2
CC1 CC0 IEDG2
Figure 28. Input Capture Timing Diagram
TIMER CLOCK
COUNTER REGISTER
FF01
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edge is rising edge.
FF02
FF03
FF03
41/109